The present technology relates to a solid-state imaging element represented by a CMOS image sensor and a camera system.
A solid-state imaging element is configured to have a photoelectric conversion unit, a charge voltage conversion unit which converts accumulated charges into a voltage, and a unit pixel with an amplifying circuit for reading the voltage of the charge voltage conversion unit.
There has been a proposed technology with regard to such a solid-state imaging element in which the opposite side (=back face) of a face where transistors are arranged is set to a light-irradiated face, and a plurality of semiconductor layers is stacked to read an output signal of pixels, thereby improving the degree of integration and parallelism.
The technology is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2006-049361.
FIG. 1 is a diagram showing a basic configuration of a solid-state imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2006-049361.
In FIG. 1, pixel cells 2 are arranged in an array shape on a first semiconductor layer 1-1 in the light sensing part side, row scanning circuits 3-1 and 3-2 are arranged in both sides of the array part, and pixel driving circuits 4-1 and 4-2 are arranged corresponding to the rows of the pixel cells 2.
FIG. 2 is a diagram showing an example of a pixel of a CMOS image sensor which includes four transistors.
The pixel cells 2 include a photoelectric conversion unit (photoelectric conversion element) 21 composed of, for example, a photodiode (PD).
In addition, the pixel cells 2 include four transistors including a transfer transistor 22, a reset transistor 23, an amplifying transistor 24, and a selection transistor 25 for the one photoelectric conversion unit 21 as active elements.
The photoelectric conversion unit 21 performs photoelectric conversion of incident light into charges (herein, electrons) in an amount corresponding to the quantity of the light.
The transfer transistor 22 is connected between the photoelectric conversion unit 21 and a floating diffusion FD as an output node, and the gate thereof (transfer gate) is given a transfer signal TRG that is a control signal through a transfer control line LTRG.
Accordingly, the transfer transistor 22 transfers the electrons photoelectrically converted in the photoelectric conversion unit 21 to the floating diffusion FD.
The reset transistor 23 is connected between a power supply line LVDD and the floating diffusion FD, and the gate thereof is given a reset signal RST that is a control signal through a reset control line LRST.
Accordingly, the reset transistor 23 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD.
The gate of the amplifying transistor 24 is connected to the floating diffusion FD. The amplifying transistor 24 is connected to an output signal line 6 through the selection transistor 25, and constitutes a source follower as a constant current source outside the pixel part.
The amplifying transistor 24 and the selection transistor 25 form an amplifying circuit 7.
In addition, a selection signal SEL that is a control signal is given to the gate of the selection transistor 25 through a selection control line LSEL according to an address signal to turn on the selection transistor 25.
If the selection transistor 25 is turned on, the amplifying transistor 24 amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to the output signal line 6.
FIG. 3 is a diagram showing an example of pixel sharing of a COMS image sensor.
In this configuration, four pixel cells 2-1 to 2-4 having each of photoelectric conversion elements 21-1 to 21-4 and transfer transistors 22-1 to 22-4 share the floating diffusion FD, the reset transistor 23, and the amplifying circuit 7.
In the solid-state imaging element, the pixel cells of FIG. 2 that have one amplifying circuit 7 for one photoelectric conversion unit 21 formed on the first semiconductor layer 1-1, the pixel cells of FIG. 3 that have one amplifying circuit 7 for a plurality of photoelectric conversion units 21, or the like is applied as shown in FIG. 1.
In addition, the solid-state imaging element in Japanese Unexamined Patent Application Publication No. 2006-049361 has a structure in which stack-connecting terminals (micro-bumps or through holes VIA) 8 that propagate signals to a different stacked second semiconductor layer 1-2 are connected in the pixel cells 2.
In other words, each of the stack-connecting terminals 8 is connected to the amplifying circuit 7 that reads signals.
In the examples of FIGS. 2 and 3, a bias transistor (load MOS) 9 that functions as a constant current source of a source follower is formed on the second semiconductor layer 1-2.